Researchers Design True 3D Processor

Rob Williams

Editor-in-Chief
Staff member
Moderator
From our front-page news:
The term '3D Chip' might sound a bit misleading, and it might very-well be. When I first heard the term, I thought it was another GPU processor, but '3D' is meant to be taken literally. All current processors out there now are 2D... flat, with components found to the right and left of each other. Researchers at the University of Rochester have developed what they claim to be the first true 3D processor, running at 1.4GHz.

A true 3D processor is one that has stacked components, rather than the side-by-side components found on all current chips. The benefits would be better efficiency, better performance and a far better footprint. One researcher noted that while we will hit a barrier with horizontal chips, vertical chips will scale indefinitely. I can see it now... installing a pole rather than a flat piece of silicon.

Of course things shouldn't get that bad, but the prospect of a 3D chip is an interesting one. What would concern me is the cooling-ability. How is it that a cube chip could be effectively cooled? With '2D' chips, they lay flat, and obviously that works out to our favor with cooling. A cube chip wouldn't be able to use a standard CPU cooler design, but rather something entirely different. Regardless, there are obvious hurdles, but it's an interesting prospect nonetheless.

intel_nehalem_die_shot_062408.jpg

The hardest part according to the researchers is getting the levels of the chip to properly interact. Professor Friedman compares the problem to a scenario where a standard microprocessor is like the U.S. traffic system, and then the 3D processor is like 3 or more U.S. traffic systems stacked atop each other and expected to coordinate traffic between levels. He says the problem is even tougher as the processors are different, so it’s more like stacking the U.S., China, and India, where traffic laws are different, atop each other.


Source: University of Rochester Press Release , Via: DailyTech
 

Kougar

Techgage Staff
Staff member
I think I have just the answer to your cooling question... ;) http://www.dailytech.com/IBM+Scient...Process+for+3D+Stacked+Chips/article12009.htm

With 3D chips the "length" signals must travel can be shortened considerably... which allows lower latencies and much higher clockspeeds because of faster signal propagation.

The hardest part according to the researchers is getting the levels of the chip to properly interact. Professor Friedman compares the problem to a scenario where a standard microprocessor is like the U.S. traffic system, and then the 3D processor is like 3 or more U.S. traffic systems stacked atop each other and expected to coordinate traffic between levels. He says the problem is even tougher as the processors are different, so it’s more like stacking the U.S., China, and India, where traffic laws are different, atop each other.

I suspect Intel can solve this issue rather easily. They have already been solving issues similar to this with Larrabee, Nehalem, and Penryn albiet in 2D form. Nehalem will be the most "segmented", or perhaps I should say compartmentalized chip to date... they are experts at compartmentalizing their chips, and that's all they need to get a foothold with 3D designs.

They've also already managed to give each core in Nehalem its own PLL, and through some creative, new clock-gating tricks have designed a CPU that can power down parts of itself or modify individual core clockspeeds even though the entire chip uses the same power plane. Only the L3 cache has a separate power plane.

Before the world knew Core 2 Duo, people would have laughed off this ability outright saying it requires multiple power planes... And is why K10 uses a separate power plane per core plus L3. ;)
 
Last edited:

Rob Williams

Editor-in-Chief
Staff member
Moderator
Ahh thanks for the link... that's interesting. It seems a little far-fetched to happen, but I could be wrong. I wonder if there could just be small ducts for heat dissipation and allow the air to flow towards the to, then be expelled through the IHS. I don't know... I'm just glad I'm not the one in charge of figuring it out ;-)

Good points on the Intel side of things. Can others accomplish the same thing is the question. Intel seems to be ahead of everyone these days.
 
Top