It appears that there has been some mixup in communication between AMD and its partners, which resulted in a bit more ROPs on the HD 6790 card. AMD's official specs stated that this Barts GPU should be left with 800 Stream processors while the number of ROPs should be 16, or half of the fully enabled Barts GPU. Unfortunately, or luckily, some if not all partners shipped their own HD 6790 card with 24 ROPs which gives a bit more geometry punch to the HD 6790. Looks to be a good mistake there EDIT: there is an update on TPU and it looks like its a screw up on their end Update: We have discussed this with AMD and it looks like this was our mistake and the cards really have 16 ROPs. The register GPU-Z looks at to calculate the number of active ROPs indicates the number of disabled ROP units using set bits. For the case of HD 6790 two bits are set, which means two disabled units. The Barts GPU has a total of 32 ROPs in 8 units, which would leave us with 24 ROPs based on the register data: (8 [total ROPs] - 2 [disabled ROPs]) * 4 [pixels per clock per ROP] = 24. If you look at the architecture diagram above (look for the thick black box or the red box), you can see that the shader units of the GPU are split into two shader arrays and the ROPs (yellow squares next to "L2 cache") are independent from these. In reality the ROPs are located inside these shader arrays, too. As a result "two deactivated ROPs" really means "two deactivated ROPs per shader array". So the correct shader count is (4 [ROPs per shader array] - 2 [disabled ROPs per shader array]) * 2 [shader arrays] * 4 [pixels per clock per ROP] = 16!