AMD's next-gen Bulldozer - Thoughts?

[Kougar]

It is never boring in the world of CPUs. Regardless of who's on top, plans for next generations tend to excite everybody in the eco-system… if you deliver, that is. AMD had a lot of tough times of late, and lost a lot of good people due to lack of proper management. In this article, we bring you a look into the architecture that everybody in the industry has been impatiently waiting for. But this time, AMD cannot afford to fail.

The Ex-Alpha engineering teams lead by Dirk Meyer that created K7 and K8 architecture messed everything up with Barcelona/Agena and the infamous TLB-bug [Translation-Lookaside Buffer]. Shanghai/Deneb cleaned a lot of things up and AMD is back being competitive again, but Intel is pushing hard: Intel is operating in tick-tock architectural mode, and so far - AMD isn't able to answer back. K10 and K10.5 were nothing else but improvements over the K8 architecture. Last time we saw a completely new architecture from AMD, the stock market thought that an online dog-food shop was worth half a billion US$, mainstream media was touting that the world is going to end with that horrible Y2K bug... Yes, quite a long time ago. But before we dig into Bulldozer's architecture, let's set the record clear, with a simple architectural comparison between AMD and Intel.

Source: AMD's next-gen Bulldozer is a 128-bit crunching monster

 

[Kougar]

Any idea what they mean by 128bit crunching monster? Unless I misunderstand Barcelona already is 128bit and so was Core 2.

I was explained that focus of AMD's design was to increase the number of instructions processed on-the-fly, meaning that most instructions should use registers in a 64+64-bit or 32+32+32+32-bit fashion, significantly raising the IPC when compared to current K10.5 architecture. So, no "x86-128".

Um, so in other words AMD is copying Intel's Core 2 Duo design. Core 2 is 64+64 already and offers full "128bit" vector support. Link

Sandy Bridge will be something more akin to "256 bit" in 2010.

One of Sandy Bridge's most widely talked-about features is a brand-new set of 256-bit vector extensions called Advanced Vector Extensions (AVX). In addition to vector registers that are double the size of the current 128-bit SSE registers, AVX will also introduce a nondestructive three-operand format for the first time in the x86 ISA's history. Link

Then again, maybe I'm not understanding the exact meaning of 128bits... because here is Ars Technica's comparison regarding Barcelona:

It does not seem that K8L will catch up to Conroe in terms of the theoretical peak number of 128-bit SSE operations per cycle, however. K8L's two floating-point/SSE pipes give it two 128-bit SSE ops/cycle, and its FSTORE pipe can do another 128-bit SSE move per cycle, for a total of three per cycle peak. This is half of Conroe's peak theoretical throughput of six 128-bit SSE ops/cycle.

 

[Merlin]

I always thought that the AMD pipelines made the score for AMD