..And hopefully leaving very shortly.
I don't even understand how their 'perfect T-tree' is supposed to help - they say it'll 'reduce clock cycle timing by 50%'. WTF does that mean? All the timings get cut in half? So it's the motherboard that causes RAM to require higher timings?
It's going to take more than that Power-Point slide to get ASUS' T-tree to fly.
In the standard DDR3 "fly by" topology, there is a significant delay from the time that an address or command signal reaches the first DRAM on the module to the time that it reaches the last. That's a fair amount of latency across the bus that has to be accounted for in memory timings. In a "tree" design, the idea is that the command and address signals hit all of the DRAMs at the same time. Obviously there is still some latency, but it's not related to the flight time across the length of an entire module (which is a significant fraction of the address and command bit period).
The problem with a classic tree design is that it's hard to properly terminate the signals on a module. There just isn't enough room for one resistor per signal per DRAM. So, DDR2, the last memory technology to use a tree, put the termination on the motherboard. But that wasn't so great for signal quality, which put an upper limit on just how fast the modules could run.
DDR3 is a balancing act between speed, latency and signal quality. Asus' approach of "memory down" takes the best of DDR2 (the tree topology) and (I'm assuming) the best of DDR3 (termination close to the DRAMs). That makes for low latency with high data rates. Also, no connector also means no impedance discontinuities which means no reflections and no signal loss. And just as important, Asus can design the memory subsystem to be optimized for that particular topology and one particular DRAM type.
And I don't even want to get into the problems with the data and strobe nets themselves and why it's a lot easier to do things the way that Asus did.
Believe me, every time a new memory technology is introduced, we wipe the sweat from our brow and wonder how long it will be before memory goes from modules to on board. AMD has moved slightly in that direction, incorporating the memory controller into the CPU - they recognize the difficulty of moving high speed parallel signals across a PCB.
DDR3 was a pretty significant change from DDR2, particularly dealing with the tree routing problem. DDR4 will probably be an incremental change over DDR3, but after that, I would not be surprised to see things radically change, either to a fully buffered DIMM type of module or some kind of serial memory bus...and maybe even (perish the thought) on-board memory. And why not? We do it with video cards - there haven't been memory sockets on video cards for ten years or so!
